In the MOSFET structure in an early stage, certain overlapped covered parts are often provided between the gate electrode and the source electrode area and between the gate electrode and the drain electrode area, in view of alignment errors of the process. However, if the overlapped parts are excessively, large parasitic capacitances between the gate and the source and between the gate and the drain are excessively increased, thereby leading to the deterioration of high-frequency characteristics of the device (particularly, the parasitic capacitance between the gate and the drain is a Miller capacitance, and has more influence). Therefore, in order to allow the conduction of the device while the high-frequency characteristics of the device are deteriorated, the overlapped parts between the gate and the source or between the gate and the drain are required to be as small as possible and highly precise alignment is thus achieved. The self-alignment process is a newly developing process. However, with respect to a self-aligned oxide semiconductor thin film transistor in a conventional process, it is difficult to ensure the distances from the gate electrode to the source electrode and the drain electrode, and the distances from the source electrode and the drain electrode on the left and right sides to the gate electrode will be inconsistent. Therefore, it is difficult to control the characteristics of the TFT, whereas the management and control requirements for the distances from the gate electrode to the source electrode and the drain electrode are very high, with respect to the self-aligned oxide semiconductor thin film transistor.